Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.
| Published in | Journal of Electrical and Electronic Engineering (Volume 5, Issue 5) |
| DOI | 10.11648/j.jeee.20170505.11 |
| Page(s) | 156-166 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2017. Published by Science Publishing Group |
Fault Tolerance, Triple Modular Redundancy, Voter Circuit, XOR Gate, Multiplexer
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APA Style
Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. (2017). A Fault Tolerant Voter Circuit for Triple Modular Redundant System. Journal of Electrical and Electronic Engineering, 5(5), 156-166. https://doi.org/10.11648/j.jeee.20170505.11
ACS Style
Mohammed Hadifur Rahman; Shahida Rafique; Mohammad Shafiul Alam. A Fault Tolerant Voter Circuit for Triple Modular Redundant System. J. Electr. Electron. Eng. 2017, 5(5), 156-166. doi: 10.11648/j.jeee.20170505.11
AMA Style
Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. A Fault Tolerant Voter Circuit for Triple Modular Redundant System. J Electr Electron Eng. 2017;5(5):156-166. doi: 10.11648/j.jeee.20170505.11
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Download@article{10.11648/j.jeee.20170505.11,
author = {Mohammed Hadifur Rahman and Shahida Rafique and Mohammad Shafiul Alam},
title = {A Fault Tolerant Voter Circuit for Triple Modular Redundant System},
journal = {Journal of Electrical and Electronic Engineering},
volume = {5},
number = {5},
pages = {156-166},
doi = {10.11648/j.jeee.20170505.11},
url = {https://doi.org/10.11648/j.jeee.20170505.11},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20170505.11},
abstract = {Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.},
year = {2017}
}
TY - JOUR T1 - A Fault Tolerant Voter Circuit for Triple Modular Redundant System AU - Mohammed Hadifur Rahman AU - Shahida Rafique AU - Mohammad Shafiul Alam Y1 - 2017/09/05 PY - 2017 N1 - https://doi.org/10.11648/j.jeee.20170505.11 DO - 10.11648/j.jeee.20170505.11 T2 - Journal of Electrical and Electronic Engineering JF - Journal of Electrical and Electronic Engineering JO - Journal of Electrical and Electronic Engineering SP - 156 EP - 166 PB - Science Publishing Group SN - 2329-1605 UR - https://doi.org/10.11648/j.jeee.20170505.11 AB - Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly. VL - 5 IS - 5 ER -
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