Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.
| Published in | Science Journal of Circuits, Systems and Signal Processing (Volume 8, Issue 2) |
| DOI | 10.11648/j.cssp.20190802.16 |
| Page(s) | 76-81 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2019. Published by Science Publishing Group |
Carry Look-ahead Adder, 4-Bit Adder, Xor Gate, And Gate, Carry-Propagate
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APA Style
Mehedi Hasan, Moumita Sadia Islam, Muhtasim Rafid Ahmed. (2019). Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Science Journal of Circuits, Systems and Signal Processing, 8(2), 76-81. https://doi.org/10.11648/j.cssp.20190802.16
ACS Style
Mehedi Hasan; Moumita Sadia Islam; Muhtasim Rafid Ahmed. Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Sci. J. Circuits Syst. Signal Process. 2019, 8(2), 76-81. doi: 10.11648/j.cssp.20190802.16
AMA Style
Mehedi Hasan, Moumita Sadia Islam, Muhtasim Rafid Ahmed. Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms. Sci J Circuits Syst Signal Process. 2019;8(2):76-81. doi: 10.11648/j.cssp.20190802.16
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Download@article{10.11648/j.cssp.20190802.16,
author = {Mehedi Hasan and Moumita Sadia Islam and Muhtasim Rafid Ahmed},
title = {Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms},
journal = {Science Journal of Circuits, Systems and Signal Processing},
volume = {8},
number = {2},
pages = {76-81},
doi = {10.11648/j.cssp.20190802.16},
url = {https://doi.org/10.11648/j.cssp.20190802.16},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20190802.16},
abstract = {Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.},
year = {2019}
}
TY - JOUR T1 - Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms AU - Mehedi Hasan AU - Moumita Sadia Islam AU - Muhtasim Rafid Ahmed Y1 - 2019/12/27 PY - 2019 N1 - https://doi.org/10.11648/j.cssp.20190802.16 DO - 10.11648/j.cssp.20190802.16 T2 - Science Journal of Circuits, Systems and Signal Processing JF - Science Journal of Circuits, Systems and Signal Processing JO - Science Journal of Circuits, Systems and Signal Processing SP - 76 EP - 81 PB - Science Publishing Group SN - 2326-9073 UR - https://doi.org/10.11648/j.cssp.20190802.16 AB - Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements. VL - 8 IS - 2 ER -
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