Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI

Abderrezak Bekaddour; Gérard Ghibaudo

doi:doi:10.11648/j.ajmp.20221105.12

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Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI

Abderrezak Bekaddour, Gérard Ghibaudo

Published in American Journal of Modern Physics (Volume 11, Issue 5)

Received: 26 June 2022 Accepted: 11 July 2022 Published: 28 September 2022

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Abstract

Temperature dependence of the drain current of a MOSFET plays a crucial role in the device performance and power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this paper, we propose the application of a symmetric Double Gate (SDG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of SDG in a Strained Double Gate Tunnel Field Effect Transistor with an Oxide gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the SDG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics. The on-current of these devices is mainly limited by the tunneling barrier properties, and phonon scattering has only a moderate effect.

Published in	American Journal of Modern Physics (Volume 11, Issue 5)
DOI	10.11648/j.ajmp.20221105.12
Page(s)	85-91
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2022. Published by Science Publishing Group

Keywords

Variability, Microelectronics, Silicon, Nanowire, NEGF, MOSFET, Phonon

References

[1]	Koswatta SO, Lundstrom MS, Nikonov DE Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56: (2009) 456–465.
[2]	Boucart K, Ionescu AMDouble-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54: (2007) 1725–1733.
[3]	Wu J, Taur YReduction of TFET off-current and subthreshold swing by lightly doped drain. IEEE Trans Electron Devices 63: (2016) 3342–3345.
[4]	A. Bekaddour, M Pala, N. E Chabansari, G Ghibaudo “Deterministic method to evaluate the threshold voltage variability induced by discrete trap charges in Si-Nanowire FET’s” IEEE Trans Electron Devices 59, n°. 5 (2012) p. 1462-1467.
[5]	Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu “Enhanced transconductance in a double-gate graphene field-effect transistor” Solid State Electronics, Volume 141, (2018) p. 65-68.
[6]	Xin Sun, Qiang Lu, V. Moroz, H. Takeuchi, G. Gebara, and J. Wetzel, “Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap,” IEEE Electron Device Letters, vol. 29, no. 5, (2008) pp. 491-493.
[7]	F. Lime, and B. Guillaumot, “Investigation of electron and hole mobilities in MOSFETs with TiN/HfO₂/SiO₂ gate stack,” Proc. of 33rd Int. Conf. on European Solid State Device Research, 16-18, ( 2003) pp. 247-250.
[8]	S. Kubicek, J. Chen, A. Ragnarsson, R. J. Carter, V. Kaushik, and K. De Meyer, “Investigation of polySi/HfO/sub 2/gate stacks in a self-aligned 70 nm MOS process flow,” Proc. of 33rd Int. Conf. on European SolidState Device Research, 16-18, pp. 251-254.
[9]	B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Trigate fully-depleted CMOS transistors: fabrication, design and layout,” Proc. of Symp. on VLSI Technology, Digest of Technical Papers, 10-12, (2003) pp. 133-134.
[10]	M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida, and T. Numata, “Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 3, ( 2012) pp. 8-10.
[11]	Nader Shehata, Abdel-Rahman Gaber, Ahmed Naguib, Ayman E. Selmy, Hossam Hassan, Ibrahim Shoeer, Omar Ahmadien and Rewan Nabeel, “3D Mutli-gate Transistors: Concept, Operation, and Fabrication,” Journal of Electrical Engineering 3; (2015) 1-14.
[12]	Ferain, I., Colinge, C. A., and Colinge, J. P. “Multigate Transistors as the Future of Classical MetalOxide Semiconductor Field Effect Transistors.” Nature 479 (2011): 310-6.
[13]	Colinge, J. P. 2013. “3D Transistors.” Presented at International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan.

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APA Style

Abderrezak Bekaddour, Gérard Ghibaudo. (2022). Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. American Journal of Modern Physics, 11(5), 85-91. https://doi.org/10.11648/j.ajmp.20221105.12

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ACS Style

Abderrezak Bekaddour; Gérard Ghibaudo. Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. Am. J. Mod. Phys. 2022, 11(5), 85-91. doi: 10.11648/j.ajmp.20221105.12

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AMA Style

Abderrezak Bekaddour, Gérard Ghibaudo. Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. Am J Mod Phys. 2022;11(5):85-91. doi: 10.11648/j.ajmp.20221105.12

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@article{10.11648/j.ajmp.20221105.12,
  author = {Abderrezak Bekaddour and Gérard Ghibaudo},
  title = {Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI},
  journal = {American Journal of Modern Physics},
  volume = {11},
  number = {5},
  pages = {85-91},
  doi = {10.11648/j.ajmp.20221105.12},
  url = {https://doi.org/10.11648/j.ajmp.20221105.12},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajmp.20221105.12},
  abstract = {Temperature dependence of the drain current of a MOSFET plays a crucial role in the device performance and power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this paper, we propose the application of a symmetric Double Gate (SDG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of SDG in a Strained Double Gate Tunnel Field Effect Transistor with an Oxide gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the SDG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics. The on-current of these devices is mainly limited by the tunneling barrier properties, and phonon scattering has only a moderate effect.},
 year = {2022}
}

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TY  - JOUR
T1  - Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI
AU  - Abderrezak Bekaddour
AU  - Gérard Ghibaudo
Y1  - 2022/09/28
PY  - 2022
N1  - https://doi.org/10.11648/j.ajmp.20221105.12
DO  - 10.11648/j.ajmp.20221105.12
T2  - American Journal of Modern Physics
JF  - American Journal of Modern Physics
JO  - American Journal of Modern Physics
SP  - 85
EP  - 91
PB  - Science Publishing Group
SN  - 2326-8891
UR  - https://doi.org/10.11648/j.ajmp.20221105.12
AB  - Temperature dependence of the drain current of a MOSFET plays a crucial role in the device performance and power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this paper, we propose the application of a symmetric Double Gate (SDG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of SDG in a Strained Double Gate Tunnel Field Effect Transistor with an Oxide gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the SDG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics. The on-current of these devices is mainly limited by the tunneling barrier properties, and phonon scattering has only a moderate effect.
VL  - 11
IS  - 5
ER  -

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Author Information

Abderrezak Bekaddour

Department of Physics, University of Tlemcen, Tlemcen, Algeria
Gérard Ghibaudo

Institut National Polytechnique-Minatec, University of Grenoble, Grenoble, France

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APA Style

Abderrezak Bekaddour, Gérard Ghibaudo. (2022). Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. American Journal of Modern Physics, 11(5), 85-91. https://doi.org/10.11648/j.ajmp.20221105.12

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ACS Style

Abderrezak Bekaddour; Gérard Ghibaudo. Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. Am. J. Mod. Phys. 2022, 11(5), 85-91. doi: 10.11648/j.ajmp.20221105.12

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AMA Style

Abderrezak Bekaddour, Gérard Ghibaudo. Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI. Am J Mod Phys. 2022;11(5):85-91. doi: 10.11648/j.ajmp.20221105.12

Copy | Download

@article{10.11648/j.ajmp.20221105.12,
  author = {Abderrezak Bekaddour and Gérard Ghibaudo},
  title = {Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI},
  journal = {American Journal of Modern Physics},
  volume = {11},
  number = {5},
  pages = {85-91},
  doi = {10.11648/j.ajmp.20221105.12},
  url = {https://doi.org/10.11648/j.ajmp.20221105.12},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajmp.20221105.12},
  abstract = {Temperature dependence of the drain current of a MOSFET plays a crucial role in the device performance and power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this paper, we propose the application of a symmetric Double Gate (SDG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of SDG in a Strained Double Gate Tunnel Field Effect Transistor with an Oxide gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the SDG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics. The on-current of these devices is mainly limited by the tunneling barrier properties, and phonon scattering has only a moderate effect.},
 year = {2022}
}

Copy | Download

TY  - JOUR
T1  - Phonon Effect with Short Drain and Source in Nanowires DGMOSFET SI
AU  - Abderrezak Bekaddour
AU  - Gérard Ghibaudo
Y1  - 2022/09/28
PY  - 2022
N1  - https://doi.org/10.11648/j.ajmp.20221105.12
DO  - 10.11648/j.ajmp.20221105.12
T2  - American Journal of Modern Physics
JF  - American Journal of Modern Physics
JO  - American Journal of Modern Physics
SP  - 85
EP  - 91
PB  - Science Publishing Group
SN  - 2326-8891
UR  - https://doi.org/10.11648/j.ajmp.20221105.12
AB  - Temperature dependence of the drain current of a MOSFET plays a crucial role in the device performance and power dissipation has become a major obstacle in performance scaling of modern integrated circuits, and has spurred the search for devices operating at lower voltage swing. In this paper, we propose the application of a symmetric Double Gate (SDG) in a Tunnel Field Effect Transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage, and also improve the average subthreshold slope, the nature of the output characteristics and the immunity against the DIBL effects. We demonstrate that if appropriate work-functions are chosen for the gate materials on the source side and the drain side, the tunnel field effect transistor shows a significantly improved performance. We apply the technique of SDG in a Strained Double Gate Tunnel Field Effect Transistor with an Oxide gate dielectric to show an overall improvement in the characteristics of the device along with achieving a good on-current and an excellent average subthreshold slope. The results show that the SDG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses and power supply levels to achieve significant gains in the overall device characteristics. The on-current of these devices is mainly limited by the tunneling barrier properties, and phonon scattering has only a moderate effect.
VL  - 11
IS  - 5
ER  -

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